Systems and methods for bit level signal processing

ABSTRACT

This disclosure relates generally to wireless communications and, more particularly, to systems and methods for bit level processing to produce a scrambled data bit sequence that, after modulation, may produce a symbol sequence that matches a symbol sequence produced by symbol spreading. In one embodiment, a method performed by a communication device includes: encoding user data to produce a first data bit sequence; generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence; and transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequence.

TECHNICAL FIELD

This disclosure relates generally to wireless communications and, moreparticularly, to systems and methods for bit level processing to producea scrambled data bit sequence that, after modulation, may produce asymbol sequence that matches a symbol sequence produced by symbolspreading.

BACKGROUND

As the number of applications and services for digital data continues toexplode, the demands and challenges placed on network resources andoperators will continue to increase. Being able to deliver a widevariety of network performance characteristics that future services willdemand is one of the primary technical challenges faced by serviceproviders today.

Symbol level spreading has been used in code division multiple access(CDMA) systems, where long spreading sequences are applied to randomizethe inter-user and inter-cell interference. Uplink signals fromdifferent users may be spread using user-specific scrambling codes andsuperimposed with each other in shared time or frequency resources.Though user interference may be introduced by non-orthogonaltransmission, a particular quality of service can be better guaranteedwith a larger spreading factor for symbol level spreading. However,typically, the longer the spreading factor the lower the data rate and,thus, suitability for wideband services in standards such as the longterm evolution (LTE) or 5th generation (5G NR) wireless systems.

FIG. 1A is a block diagram 100 that illustrates transmitter sideprocessing. The block diagram 100 references a user data layer of anarbitrary user (e.g., the ith user). At block 102, the transmitter sideprocessing may start with user data that is processed by a channelencoder (e.g processed by encoding). At block 104, the user data may besubsequently processed by rate matching. At block 106, the user data maybe subsequently processed by bit interleaving. At block 108, the userdata may be subsequently processed by bit scrambling. At block 110, theuser data may be subsequently processed by a modulator. At block 112,the user data may be subsequently processed by resource mapping beforetransmission.

FIG. 1B is a block diagram 150 that illustrates transmitter sidenon-orthogonal multiple access (NOMA) processing. The block diagram 150references user layer data of an arbitrary user (e.g., the ith user). Atblock 152, the transmitter side processing may start with user data thatis processed by a channel encoder. At block 154, the user data may besubsequently processed by rate matching or repetition. At block 156, theuser data may be subsequently processed by user equipment (UE) specificbit interleaving or scrambling. At block 158, the user data may besubsequently processed by a UE specific modulator. At block 110, theuser data may be subsequently processed by UE specific symbol spreading.At block 112, the user data may be subsequently processed by resourcemapping before transmission.

This type of NOMA based transmitter side processing may involve channelcoding with UE-specific bit-level scrambling or interleaving,UE-specific modulation or UE-specific symbol-level spreading. This isreflected in blocks 156, 158, 160. NOMA schemes based on bit-levelprocessing may have less specification impact. For example, interleavingand scrambling processing may already be included in currentspecifications with a transmitter. Accordingly, changes in transmissionsunder a NOMA scheme may be generally directed to scrambling. Also, thedesign of scrambling bit sequences may be directed to reduce inter-userinterference. In conjunction with transmission based processing, asoft-input-soft-output (SISO) iterative decoding processes that includessoft interference cancellation may be utilized to further reduceinter-user interference at the receiver for multi-user detection.

Symbol level spreading based NOMA schemes may not change processing atthe bit level. In addition, the above referenced UE-specific spreadingsequences are mainly used for UE differentiation and interferencereduction. The de-spreading and channel equalization (with considerationof multi-user interferences) can be achieved simultaneously throughminimum mean square error (MMSE) equalization from joint code andspatial domains. For example, a single-user decoder can be utilized forbit-level processing at the receiver side. Also, no fundamental changemay be required on the receiver side to implement symbol-levelspreading.

For symbol level spreading based NOMA schemes, the cross-correlationproperty of the spreading sequences between different UEs may beimportant to overall system performance. A design target for thespreading sequences may be to meet a welch-bound equality (WBE) criteriafor cross-correlation among sequences. By meeting the WBE criteria, themean squared error (MSE) per user may be reduced under the assumption ofequal signal noise ratio (SNR) distribution among NOMA users. Statedanother way, cross-correlation may be related to spreading length andthe size of a sequence pool. For example, smaller overallcross-correlation can be achieved with a longer spreading length. Also,higher cross-correlation may be achieved when a larger sequence pool isused to accommodate more UEs at a given spreading factor.

Certain systems may have relatively lower spectral efficiency per UE anduse relatively shorter spreading lengths than other systems. Given ashorter spreading length, complex-valued sequences can provide a largersequence pool size compared with pseudo-noise (PN) sequences. Forexample, the length-L sequence with each of the element picked from {−1,1, −j, j} may have 4^(L) different sequences, while PN sequences(element picked from {−1, 1}) may have only 2^(L) different sequences.

Accordingly, symbol level spreading or symbol spreading may beintroduced to multiplex a greater number of users and to achieve ahigher sum spectral efficiency than orthogonal resource basedtransmissions. Spreading based schemes are normally operated at a symbollevel, where a low inter-user interference may be achieved by using lowcross-correlation sequences such as welch bound equality (WBE)sequences, or using low density spreading codes such as sparse codes. Aminimum mean squared error criterion with successive interferencecancellation (MMSE-SIC) receiver can be used to achieve certain levelsof interference rejection among multiple users at the symbol-level injoint code and spatial domains. However, the current standards may notsupport symbol level spreading for certain data transmissions.Therefore, there is a need to achieve the particular level of servicethat symbol spreading would provide through other techniques.

SUMMARY OF THE INVENTION

The exemplary embodiments disclosed herein are directed to solving theissues relating to one or more of the problems presented in the priorart, as well as providing additional features that will become readilyapparent by reference to the following detailed description when takenin conjunction with the accompany drawings. In accordance with variousembodiments, exemplary systems, methods, devices and computer programproducts are disclosed herein. It is understood, however, that theseembodiments are presented by way of example and not limitation, and itwill be apparent to those of ordinary skill in the art who read thepresent disclosure that various modifications to the disclosedembodiments can be made while remaining within the scope of theinvention.

In one embodiment, a method performed by a communication deviceincludes: encoding user data to produce a first data bit sequence;generating a result bit sequence based on a first scrambling bitsequence and the first data bit sequence; and transmitting a signalbased on a scrambled data bit sequence scrambled with the result bitsequence.

In a further embodiment, a method performed by a communication nodeincludes: encoding user data to produce a first data bit sequence;generating a result bit sequence based on a first scrambling bitsequence and the first data bit sequence; and transmitting a signalbased on a scrambled data bit sequence scrambled with the result bitsequence.

In a further embodiments, a communication device includes: at least oneprocessor configured to: encode user data to produce a first data bitsequence, and generate a result bit sequence based on a first scramblingbit sequence and the first data bit sequence; and at least onetransmitter configured to: transmit a signal based on a scrambled databit sequence scrambled with the result bit sequence.

In a further embodiment, a communication node includes: at least oneprocessor configured to: encode user data to produce a first data bitsequence, and generate a result bit sequence based on a first scramblingbit sequence and the first data bit sequence; and at least onetransmitter configured to: transmit a signal based on a scrambled databit sequence scrambled with the result bit sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

Various exemplary embodiments of the invention are described in detailbelow with reference to the following Figures. The drawings are providedfor purposes of illustration only and merely depict exemplaryembodiments of the invention to facilitate the reader's understanding ofthe invention. Therefore, the drawings should not be considered limitingof the breadth, scope, or applicability of the invention. It should benoted that for clarity and ease of illustration these drawings are notnecessarily drawn to scale.

FIG. 1A is a block diagram that illustrates transmitter side processing.

FIG. 1B is a block diagram that illustrates transmitter sidenon-orthogonal multiple access (NOMA) processing.

FIG. 2 illustrates an exemplary wireless communication network in whichtechniques disclosed herein may be implemented, in accordance with anembodiment of the present disclosure.

FIG. 3 illustrates block diagrams of an exemplary system including abase station (BS) and user equipment (UE), in accordance with someembodiments.

FIG. 4 is a block diagram illustrating signal processing for symbollevel spreading, in accordance with various embodiments.

FIG. 5 is a block diagram illustrating bit level signal processing toproduce a same symbol sequence for resource mapping as that of FIG. 4,in accordance with various embodiments.

FIG. 7 is an illustration of a bit to symbol mapping for a 16 statequadrature amplitude modulation (16QAM) constellation used in updatedscrambling bit sequence processing, in accordance with some embodiments.

FIG. 8 is an illustration of a bit to symbol mapping for a 64 statequadrature amplitude modulation (64QAM) constellation used in updatedscrambling bit sequence processing, in accordance with some embodiments.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Various exemplary embodiments of the invention are described below withreference to the accompanying figures to enable a person of ordinaryskill in the art to make and use the invention. As would be apparent tothose of ordinary skill in the art, after reading the presentdisclosure, various changes or modifications to the examples describedherein can be made without departing from the scope of the invention.Thus, the present invention is not limited to the exemplary embodimentsand applications described and illustrated herein. Additionally, thespecific order or hierarchy of steps in the methods disclosed herein aremerely exemplary approaches. Based upon design preferences, the specificorder or hierarchy of steps of the disclosed methods or processes can bere-arranged while remaining within the scope of the present invention.Thus, those of ordinary skill in the art will understand that themethods and techniques disclosed herein present various steps or acts ina sample order, and the invention is not limited to the specific orderor hierarchy presented unless expressly stated otherwise.

The discussion below may refer to functional entities or processes whichare similar to those mentioned above with respect to conventionalcommunication systems. As would be understood by persons of ordinaryskill in the art, however, such conventional functional entities orprocesses do not perform the functions described below, and therefore,would need to be modified or specifically configured to perform one ormore of the operations described below. Additionally, persons of skillin the art would be enabled to configure functional entities to performthe operations described herein after reading the present disclosure.

The discussion below may refer to functional entities, such as a BS, UE,core network, cell, etc. (either in physical or virtual form), which aresimilar to those mentioned above with respect to conventionalcommunication systems. As would be understood by persons of ordinaryskill in the art, however, such conventional functional entities do notperform the functions described below, and therefore, would need to bemodified or specifically configured to perform one or more of theoperations described below. Additionally, persons of skill in the artwould be enabled to configure functional entities to perform theoperations described herein after reading the present disclosure. Theterm “configured” as used herein with respect to a specified operationor function refers to a system, device, component, circuit, structure,machine, etc. that is physically or virtually constructed, programmedand/or arranged to perform the specified operation or function.

FIG. 2 illustrates an exemplary wireless communication network 200 inwhich techniques disclosed herein may be implemented, in accordance withan embodiment of the present disclosure. The exemplary communicationnetwork 200 may overlay a geographic area 201 and include a base station(BS) 202 and a user equipment (UE) device 204 (e.g., UE 204) that cancommunicate with each other via a communication link 210 (e.g., awireless communication channel), and a cluster of notional cells 226,230, 232, 234, 236, 238 and 240. In FIG. 2, the BS 202 and UE 204 arecontained within the geographic boundary of cell 226. Each of the othercells 230, 232, 234, 236, 238 and 240 may include at least one basestation (BS) operating at its allocated bandwidth to provide adequateradio coverage to its intended users. For example, the BS 202 mayoperate at an allocated channel transmission bandwidth to provideadequate coverage to the UE 204. The BS 202 and the UE 204 maycommunicate via a downlink radio frame 241 for BS/UE communications, andan uplink radio frame 243 for BS/UE communications respectively. Eachradio frame 245/247 may be further divided into sub-frames 249/251 whichmay include data symbols 253/255. Accordingly, reference to a cell mayalso be a short hand reference to a BS with an associated cellularcoverage region or area.

In the present disclosure, the base station (BS) 202 and user equipment(UE) 204 are described herein as non-limiting examples of “communicationnodes,” generally, which can practice the methods disclosed herein. Suchcommunication nodes may be capable of wireless and/or wiredcommunications, in accordance with various embodiments of the invention.Each of these communication nodes may be a transmitter in one situationand a receiver in another situation. For example, a BS 202 may transmitto a UE 204, such as during a downlink (DL), discussed further below.Therefore, the BS 202 may be a transmitter and the UE 204 may be areceiver. However, in another situation (such as during an uplink (UL),described further below) the UE 204 may be a transmitter and the BS 202may be a receiver. Accordingly, both the BS 202 and the UE 204 may be areceiver or a transmitter. In certain embodiments, a communicationdevice may refer to a UE while a communication node may refer to a BS todifferentiate from the UE. Furthermore, the term “downlink (DL)” and“uplink (UL)” may be relative terms that describe a relative directionof information flow relative to a BS and/or UE's orientation within asystem.

FIG. 3 illustrates block diagrams of an exemplary system 300 including abase station (BS) 302 and user equipment (UE) 304 for transmitting andreceiving wireless communication signals, e.g., OFDMIOFDMA signals,between each other. The system 300 may include components and elementsconfigured to support known or conventional operating features that neednot be described in detail herein. In one exemplary embodiment, system300 can be used to transmit and receive data symbols in a wirelesscommunication environment such as the wireless communication environment200 of FIG. 2, as described above.

The BS 302 includes a BS transceiver module 310, a BS antenna 312, a BSprocessor module 314, a BS memory module 316, and a networkcommunication module 318, each module being coupled and interconnectedwith one another as necessary via a data communication bus 320. Incertain embodiments, the data communications bus 320 may be implementedas a wireless bus from which modules or other portions of the BS 302 maycommunicate with each other wirelessly.

The UE 304 includes a UE transceiver module 330, a UE antenna 332, a UEmemory module 334, and a UE processor module 336, each module beingcoupled and interconnected with one another via a data communication bus340. The BS 302 communicates with the UE 304 via a communication channel(e.g., link) 350, which can be any wireless channel or other mediumknown in the art suitable for transmission of data as described herein.

As would be understood by persons of ordinary skill in the art, system300 may further include any number of modules other than the modulesshown in FIG. 2. Those skilled in the art will understand that thevarious illustrative blocks, modules, circuits, and processing logicdescribed in connection with the embodiments disclosed herein may beimplemented in hardware, computer-readable software, firmware, or anypractical combination thereof. To clearly illustrate thisinterchangeability and compatibility of hardware, firmware, andsoftware, various illustrative components, blocks, modules, circuits,and steps are described generally in terms of their functionality.Whether such functionality is implemented as hardware, firmware, orsoftware depends upon the particular application and design constraintsimposed on the overall system. Those familiar with the conceptsdescribed herein may implement such functionality in a suitable mannerfor each particular application, but such implementation decisionsshould not be interpreted as limiting the scope of the presentinvention.

In accordance with some embodiments, UE transceiver 330 may include a RFtransmitter and receiver circuitry that are each coupled to the antenna332. A duplex switch (not shown) may alternatively couple a transmitteror receiver to the uplink antenna in time duplex fashion. Similarly, inaccordance with some embodiments, the BS transceiver 310 may include RFtransmitter and receiver circuitry that are each coupled to the antenna312. A duplex switch may alternatively couple a transmitter or receiverto the antenna 312 in time duplex fashion. The operations of the twotransceivers 310 and 330 are coordinated in time such that the receiveris coupled to the antenna 332 for reception of transmissions over thewireless transmission link 350 at the same time that the transmitter iscoupled to the antenna 312. Preferably there is close timesynchronization with only a minimal guard time between changes in duplexdirection.

The UE transceiver 330 and the base station transceiver 310 areconfigured to communicate via the wireless data communication link 350,and cooperate with a suitably configured RF antenna arrangement 312/332that can support a particular wireless communication protocol andmodulation scheme. In some exemplary embodiments, the UE transceiver 308and the base station transceiver 310 are configured to support industrystandards such as the Long Term Evolution (LTE) and emerging 5G and NewRadio (NR) standards, and the like. It is understood, however, that theinvention is not necessarily limited in application to a particularstandard and associated protocols. Rather, the UE transceiver 330 andthe base station transceiver 310 may be configured to support alternate,or additional, wireless data communication protocols, including futurestandards or variations thereof.

In accordance with various embodiments, the BS 302 may be a nextgeneration nodeB (gNodeB or gNB), serving gNB, target gNB, transmissionreception point (TRP), evolved node B (eNB), a serving eNB, a targeteNB, a femto station, or a pico station, for example. In someembodiments, the UE 304 may be embodied in various types of user devicessuch as a mobile phone, a smart phone, a personal digital assistant(PDA), tablet, laptop computer, wearable computing device, etc. Theprocessor modules 314 and 336 may be implemented, or realized, with ageneral purpose processor, a content addressable memory, a digitalsignal processor, an application specific integrated circuit, a fieldprogrammable gate array, any suitable programmable logic device,discrete gate or transistor logic, discrete hardware components, or anycombination thereof, designed to perform the functions described herein.In this manner, a processor may be realized as a microprocessor, acontroller, a microcontroller, a state machine, or the like. A processormay also be implemented as a combination of computing devices, e.g., acombination of a digital signal processor and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a digital signal processor core, or any other such configuration.

Furthermore, the steps of a method or algorithm described in connectionwith the embodiments disclosed herein may be embodied directly inhardware, in firmware, in a software module executed by processormodules 314 and 336, respectively, or in any practical combinationthereof. The memory modules 316 and 334 may be realized as RAM memory,flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a harddisk, a removable disk, a CD-ROM, or any other form of storage mediumknown in the art. In this regard, memory modules 316 and 334 may becoupled to the processor modules 314 and 336, respectively, such thatthe processors modules 314 and 336 can read information from, and writeinformation to, memory modules 316 and 334, respectively. The memorymodules 316 and 334 may also be integrated into their respectiveprocessor modules 314 and 336. In some embodiments, the memory modules316 and 334 may each include a cache memory for storing temporaryvariables or other intermediate information during execution ofinstructions to be executed by processor modules 314 and 336,respectively. Memory modules 316 and 334 may also each includenon-volatile memory or non-transitory memory for storing instructions(e.g., computer readable instructions) to be executed by the processormodules 314 and 336, respectively.

The network communication module 318 generally represents the hardware,software, firmware, processing logic, and/or other components of the BS302 that enable bi-directional communication between base stationtransceiver 310 and other network components and communication nodesconfigured to communication with the BS 302. For example, networkcommunication module 318 may be configured to support internet or WiMAXtraffic. In a typical deployment, without limitation, networkcommunication module 318 provides an 802.3 Ethernet interface such thatbase station transceiver 310 can communicate with a conventionalEthernet based computer network. In this manner, the networkcommunication module 318 may include a physical interface for connectionto the computer network (e.g., Mobile Switching Center (MSC)).

FIG. 4 is a block diagram 400 illustrating signal processing for symbollevel spreading, in accordance with various embodiments. At block 402,data bits may be processed by a channel encoded to produce a codedbinary data bit sequence {right arrow over (c)}. At block 404, the codedbinary data bit sequence {right arrow over (c)} as output by block 402may be modulated as a symbol sequence M({right arrow over (c)}) througha modulator (e.g., modulation via quadrature phase shift keying (QPSK),or any type of quadrature amplitude modulation (M-QAM)). At block 406,the symbol sequence M({right arrow over (c)}) as output by block 404 maybe spread in a UE-specific manner with the length-L spreading sequence{s₁, s₂, . . . , s_(L)}. At block 408, the spread modulated symbolsequence as output by block 406 may be mapped to resource elements fortransmission.

FIG. 5 is a block diagram 500 illustrating bit level signal processingto produce a same symbol sequence for resource mapping as that of FIG.4, in accordance with various embodiments. At block 502, data bits maybe processed by a channel encoder to produce a coded binary data bitsequence {right arrow over (c)}. At block 504, the coded binary data bitsequence {right arrow over (c)} may undergo bit level repetition (e.g.,duplication) to achieve a same length as a length-L spreading sequence{s₁, s₂, . . . , s_(L)}. Stated another way, at block 504, the codedbinary data bit sequence c may undergo bit level repetition by an “L”number of times that is equivalent to the length value “L” of the abovereferenced length-L spreading sequence {s₁, s₂, . . . , s_(L)}. At block506, after bit level repetition, the output of block 504 may undergo adeliberate scrambling (e.g., as part of updated scrambling bit sequenceprocessing or updated data bit sequence processing, as will be discussedfurther below) by a scrambling bit sequence. At block 508, the scrambledoutput of block 506 may undergo modulation into a symbol sequence. Atblock 510, the modulated output of block 508 (e.g., a modulatedscrambled data bit sequence) may be mapped to resource elements fortransmission.

In certain embodiments, block diagram 500 may achieve the followingrelationship:

M({right arrow over (c)})·s _(l) =M({right arrow over (c)} _(l)), foreach l=1, . . . ,L.

where M({right arrow over (c)}) is a modulated coded binary data bitsequence, s_(l) is a scrambling bit sequence, M({right arrow over (c)}₁)is a modulated scrambled data bit sequence, 1 is an index value, and Lis a length of a desired spreading sequence. Also, symbol levelspreading with complex-valued elements picked from {1, −1, j, −j} mayrepresents a modulation constellation rotated by angles {0, pi, pi/2,−pi/2}. Accordingly, the relationship between a modulated coded binarydata bit sequence that is symbol spread, notated as M_(l)({right arrowover (c)}), and M({right arrow over (c)}) may be expressed as follows:

$\quad\left\{ \begin{matrix}{{{M_{l}\left( \overset{\rightarrow}{c} \right)} = {M\left( \overset{\rightarrow}{c} \right)}},} & {{{{if}\mspace{14mu} s_{l}} = 1};} \\{{{M_{l}\left( \overset{\rightarrow}{c} \right)} = {{M\left( \overset{\rightarrow}{c} \right)}*e^{{- \pi}j}}},} & {{{{if}\mspace{14mu} s_{l}} = {- 1}};} \\{{{M_{l}\left( \overset{\rightarrow}{c} \right)} = {{M\left( \overset{\rightarrow}{c} \right)}*e^{\frac{\pi}{2}j}}},} & {{{{if}\mspace{14mu} s_{l}} = j};} \\{{{M_{l}\left( \overset{\rightarrow}{c} \right)} = {{M\left( \overset{\rightarrow}{c} \right)}*e^{{- \frac{\pi}{2}}j}}},} & {{{{if}\mspace{14mu} s_{1}} = {- j}};}\end{matrix} \right.$

As noted above, a data bit sequence may be scrambled to produce ascrambled data bit sequence that is then modulated to produce a symbolsequence. This symbol sequence may be equivalent to another symbolsequence produced by having the same data bit sequence being directlymodulated and symbol spread.

These techniques to produce such a symbol sequence without symbol levelspreading may be termed either as updated scrambling bit sequenceprocessing or updated data bit sequence processing. Updated scramblingbit sequence processing may include generating an updated scrambling bitsequence with a scrambling bit sequence and a data bit sequence. Thenthe updated scrambling bit sequence is used to scramble the data bitsequence. Updated data bit sequence processing may include generating anupdated data bit sequence with a scrambling bit sequence and a data bitsequence. Then the updated data bit sequence is scrambled with thescrambling bit sequence.

For both updated scrambling bit sequence processing and updated data bitsequence processing, user data may be encoded to produce a first databit sequence (e.g., an original data bit sequence). Then, an exclusiveOR (XOR) operation may be performed on two. adjacent most significantbits of a first scrambling bit sequence (e.g., an original scramblingbit sequence) to produce a scrambling bit value. Then, the XOR operationmay be performed on each two adjacent bits of the first data bitsequence to produce a second data bit sequence. Then, an AND operationmay be performed on the scrambling bit value and the second data bitsequence to produce a result bit sequence. This result bit sequence maybe utilized to produce the scrambled data bit sequence referenced above.

However, for updated scrambling bit sequence processing, an XORoperation may be performed on the result bit sequence with eachcorresponding two adjacent bits of the first scrambling bit sequence toproduce an updated scrambling bit sequence. Then, the first data bitsequence may be scrambled with the updated scrambling bit sequence toproduce the scrambled data bit sequence.

Also, for updated data bit sequence processing, an XOR operation may beperformed on the result bit sequence with each corresponding twoadjacent bits of the first data bit sequence to produce an updated databit sequence. Then, the updated data bit sequence may be scrambled withthe first scrambling bit sequence to produce the scrambled data bitsequence referenced above.

Stated another way, in one embodiment of updated scrambling bit sequenceprocessing, the first two scrambling bits of a scrambling bit sequence(e.g., a first scrambling bit sequence) for each symbol may be XORed toget a scrambling-XOR-bit-1 (e.g., a scrambling bit value). Then each twobits of the data bit sequence (e.g., a first data bit sequence) for eachsymbol are XORed to get a data-XOR-bit-k (e.g., a second data bitsequence). Then, the scrambling-XOR-bit-1 and the data-XOR-bit-k areANDed to get a result-bit-k (e.g., a result bit sequence). Then theresult-bit-k is XORed with the corresponding two bits of the scramblingbit sequence for the same symbol to generate the updated scrambling bitsequence. Then the updated scrambling bit sequence is used to scramblethe data bit sequence in a conventional manner.

For example, let {b₀, b₁,b₂,b₃, . . . b_(2K-2),b_(2K-1)} be the firstdata bit sequence. Also, let {a₀, a₁, a₂, a₃, . . . a_(2K-2), a_(2K-1)}be the first scrambling bit sequence. The scrambling-XOR-bit-1 (e.g.,the scrambling bit value) Xs₁ is calculated by Xs₁=a₀⊕a₁. Also, thedata-XOR-bit-k (e.g., the second data bit sequence) Xd_(k) is calculatedby Xd_(k)=b_(2k-2)⊕b_(2k-1), k=1, 2, . . . K. The result-bit-k (e.g., aresult bit sequence) R_(k) is calculated by R_(k)=Xs₁×Xd_(k).Furthermore, the updated scrambling bit sequence is produced or updatedby ā_(2k-2)=a_(2k-2) ⊕R_(k), ā_(2k-1)=a_(2k-1)⊕R_(k). Then the firstdata bit sequence is scrambled by the updated scrambling bit sequence toget the scrambled data bit sequence: {{tilde over (b)}₀, {tilde over(b)}₁, . . . {tilde over (b)}_(2K-2), {tilde over (b)}_(2K-1)}={b₀, b₁,. . . b_(2K-2), b_(2K-1)}⊕{ā₀, ā₁, . . . ā_(2K-2), ā_(2K-1)}.

In one embodiment of updated data bit sequence processing, the first twoscrambling bits of a scrambling bit sequence (e.g., a first scramblingbit sequence) for each symbol are XORed to get a scrambling-XOR-bit-1(e.g., a scrambling bit value). Then, for each two bits of the data bitsequence (e.g., first data bit sequence) for each symbol are XORed toget a data-XOR-bit-k (e.g., a second data bit sequence). Then, thescrambling-XOR-bit-1 and the data-XOR-bit-k are ANDed to get theresult-bit-k (e.g., a result bit sequence). Then, the result-bit-k isXORed with the corresponding two bits of the data bit sequence for thesame symbol to generate the updated data bit sequence. Then the updateddata bit sequence is scrambled with the scrambling bit sequence in aconventional manner.

For example, let {b₀, b₁, b₂, b₃, . . . b_(2K-2), b_(2K-1)} be the firstdata bit sequence. Also, let {a₀, a₁, a₂,a₃, . . . a_(2K-2), a_(2K-1)}be the first bit scrambling bit sequence. The scrambling-XOR-bit-1(e.g., the scrambling bit value) Xs₁ is calculated by Xs₁=a₀ ⊕+a₁. Thedata-XOR-bit-k (e.g., the second data bit sequence) Xd_(k) is calculatedby Xd_(k)=b_(2k-2)⊕b_(2k-1), k=1, 2, . . . K. The result-bit-k (e.g.,the result bit sequence) R_(k) is calculated by R_(k)=Xs₁×Xd_(k).Furthermore, the updated data bit sequence is produced or updated by b_(2k-2)=b_(2k-2)⊕R_(k), b _(2k-1)=b_(2k-1) ⊕R_(k). Then the updated databit sequence is scrambled with the scrambling bit sequence as in aconventional manner to get the scrambled data bit sequence: {{tilde over(b)}₀, {tilde over (b)}₁, . . . {tilde over (b)}_(2K-2), {tilde over(b)}_(2K-1)}={b ₀, b ₁, . . . b _(2K-2), b _(2K-1)}⊕{a₀,a₁, . . .a_(2K-2), a_(2K-1)}.

A number of updated scrambling bit sequence processing embodiments aredescribed with the following figures. FIG. 6 is an illustration of a bitto symbol mapping constellation used in updated scrambling bit sequenceprocessing, in accordance with some embodiments. The QPSK constellation600 denotes having each two consecutive coded binary bits {right arrowover (c)}={b₀, b₁} mapped to one symbol and expressed with the followingequation:

${M\left( \overset{\rightarrow}{c} \right)} = {{\frac{1}{\sqrt{2}}\left\lbrack {\left( {1 - {2b_{0}}} \right) + {j\left( {1 - {2b_{1}}} \right)}} \right\rbrack}.}$

In the above equation, b_(2l) denotes the sign of the real part of thecomplex-valued modulation symbol, and b_(2l+1) denotes the sign of theimaginary part (e.g., “imag”) of the complex-valued modulation symbol.As illustrated, the QPSK constellation 600 may be symmetrical about twoaxes.

A scrambling bit sequence for QPSK (corresponding to spreading values{1}, {−1}, {j}, {−j} may be {0,0}, {1,1}, {1,0} and {0,1}. Thus, ifs_(l)=1, then the original (e.g., first) scrambling bit sequence may be{0,0}. Thus, the scrambling-XOR-bit may be 0 and the result-bit-1 may be0 and the updated scrambling bit sequence may be {0,0} irrespective ofthe data bit sequence. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{˜}{b}}_{0},\overset{˜}{b_{1}}} \right\} \right)} = {{M\left( {\left\{ {b_{0}\ ,b_{1}} \right\} \oplus \left\{ {0,0} \right\}} \right)} = {M\left( \left\{ {b_{0},b_{1}} \right\} \right)}}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {\left( {1 - {2b_{0}}} \right) + {j\left( {1 - {2b_{1}}} \right)}} \right\rbrack} = {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*1}}}\end{matrix}$

In certain embodiments, if s_(l)=−1, then the original (e.g., first)scrambling bit sequence is {1,1}. Thus, the scrambling-XOR-bit is 0 andthe result-bit-1 is 0 and the updated scrambling bit sequence is {1,1}irrespective of the data bit sequence. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {1,1} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},{1 - b_{1}}} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {\left( {1 - {2\left( {1 - b_{0}} \right)}} \right) + {j\left( {1 - {2\left( {1 - b_{1}} \right)}} \right\rbrack}} \right\rbrack}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*{- 1}}}\end{matrix}$

In certain embodiments, if s_(l)=j, then the original (e.g., first)scrambling bit sequence is {1,0}, so the scrambling-XOR-bit is 1. Also,if {b₀,b₁}={0,0}, then the data-XOR-bit-1 is 0, and the result-bit-1 is0. Thus, the updated scrambling bit sequence is {1,0} and the scrambledbit sequence of this symbol is {1,0}, which can be modulated to a symbolequivalent to the symbol modulated by {0,0} and multiplied with j. Thismay be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {1,0} \right\}} \right)}} \\{= {M\left( {\left\{ {0,0} \right\} \oplus \left\{ {1,0} \right\}} \right)}} \\{= {M\left( \left\{ {1,0} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {{- 1} + j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {1 + j} \right\rbrack}*j}} \\{= {{M\left( \left\{ {0,0} \right\} \right)}*j}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*j}}\end{matrix}$

However, if {b₀,b₁}={0,1}, then the data-XOR-bit-1 is 1, and theresult-bit-1 is 1. Thus, the updated scrambling bit sequence is {0,1}and the scrambled bit sequence of this symbol is {0,0}, which can bemodulated to a symbol equivalent to the symbol modulated by {0,1} andmultiplied with j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {0,1} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( \left\{ {0,0} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {1 + j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {1 - j} \right\rbrack}*j}} \\{= {{M\left( \left\{ {0,1} \right\} \right)}*j}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*j}}\end{matrix}$

However, if {b₀,b₁}={1,0}, then the data-XOR-bit-1 is 1, and theresult-bit-1 is 1. Thus, the updated scrambling bit sequence is {0,1}and the scrambled bit sequence of this symbol is {1,1}, which can bemodulated to a symbol equivalent to the symbol modulated by {1,0} andmultiplied with j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {1,0} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( \left\{ {1,1} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {{- 1} - j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {{- 1} + j} \right\rbrack}*j}} \\{= {{M\left( \left\{ {1,0} \right\} \right)}*j}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*j}}\end{matrix}$

However, if {b₀,b₁}={1,1}, then the data-XOR-bit-1 is 0, and theresult-bit-1 is 0. Thus, the updated scrambling bit sequence is {1,0}and the scrambled bit sequence of this symbol is {0,1}, which can bemodulated to a symbol equivalent to the symbol modulated by {1,1} andmultiplied with j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {1,1} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( \left\{ {1,1} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {{- 1} - j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {{- 1} + j} \right\rbrack}*j}} \\{= {{M\left( \left\{ {1,0} \right\} \right)}*j}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*j}}\end{matrix}$

In certain embodiments, if s_(l)=−j, then the original scrambling bitsequence is {0,1}, and the scrambling-XOR-bit is 1. Also, if{b₀,b₁}={0,0}, then the data-XOR-bit-1 is 0, and the result-bit-1 is 0.Thus, the updated scrambling bit sequence is {0,1} and the scrambled bitsequence of this symbol is {0,1}, which can be modulated to a symbolequivalent to the symbol modulated by {0,0} and multiplied with −j. Thismay be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {0,0} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( \left\{ {0,1} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {1 - j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {1 + j} \right\rbrack}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {0,0} \right\} \right)}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*\left( {- j} \right)}}\end{matrix}$

However, if {b₀,b₁}={0,1}, then the data-XOR-bit-1 is 1, and theresult-bit-1 is 1. Thus, the updated scrambling bit sequence is {1,0}and the scrambled bit sequence of this symbol is {1,1}, which can bemodulated to a symbol equivalent to the symbol modulated by {0,1} andmultiplied with −j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {0,1} \right\} \oplus \left\{ {1,0} \right\}} \right)}} \\{= {M\left( \left\{ {1,1} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {{- 1} - j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {1 - j} \right\rbrack}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {0,1} \right\} \right)}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*\left( {- j} \right)}}\end{matrix}$

However, if {b₀,b₁}={1,0}, then the data-XOR-bit-1 is 1, and theresult-bit-1 is 1. Thus, the updated scrambling bit sequence is {1,0}and the scrambled bit sequence of this symbol is {0,0}, which can bemodulated to a symbol equivalent to the symbol modulated by {1,0} andmultiplied with −j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1}} \right\}} \right)}} \\{= {M\left( {\left\{ {1,0} \right\} \oplus \left\{ {1,0} \right\}} \right)}} \\{= {M\left( \left\{ {0,0} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {1 + j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {{- 1} + j} \right\rbrack}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {1,0} \right\} \right)}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1}} \right\} \right)}*\left( {- j} \right)}}\end{matrix}$

However, if {b₀, b₁}={1,1}, then the data-XOR-bit-1 is 0, and theresult-bit-1 is 0. Thus, the updated scrambling bit sequence is {0,1}and the scrambled bit sequence of this symbol is {1,0}, which can bemodulated to a symbol equivalent to the symbol modulated by {1,1} andmultiplied with −j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1}} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( {\left\{ {1,1} \right\} \oplus \left\{ {0,1} \right\}} \right)}} \\{= {M\left( \left\{ {1,0} \right\} \right)}} \\{= {\frac{1}{\sqrt{2}}\left\lbrack {{- 1} + j} \right\rbrack}} \\{= {{\frac{1}{\sqrt{2}}\left\lbrack {{- 1} - j} \right\rbrack}*\left( {- j} \right)}} \\{= {{M\left( \left\{ {1,1} \right\} \right)}*\left( {- j} \right)}}\end{matrix}$

FIG. 7 is an illustration of a bit to symbol mapping for a 16 statequadrature amplitude modulation (16QAM) constellation used in updatedscrambling bit sequence processing, in accordance with some embodiments.The 16QAM constellation 700 denotes having each four consecutive codedbinary bits {right arrow over (c)}={b₀, b₁, b₂, b₃} mapped to onesymbol, as expressed with the following equation:

${M\left( \overset{\rightarrow}{c} \right)} = {\frac{1}{\sqrt{10}}{\left\{ {{\left( {1 - {2b_{0}}} \right)\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack} + {{j\left( {1 - {2b_{1}}} \right)}\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack}} \right\}.}}$

In the above equation, b₀ denotes the sign of the real part of thecomplex-valued modulation symbol, b₁ denotes the sign of the imaginarypart, b₂ is used to distinguish the inner ring or outer ring of the realpart, and b₃ is used to distinguish the inner ring or outer ring of theimaginary part of the complex-valued modulation symbol. Accordingly, thescrambling bit sequence corresponding to a 16QAM spreading value{1},{−1}, {j}, {−j} is {0,0,0,0}, {1,1,0,0}, {1,0,0,0} and {0,1,0,0}.

In certain embodiments, if s_(l)=1, then the original scrambling bitsequence is {0,0,0,0}. Thus, the scrambling-XOR-bit is 0 and theresult-bit-1 is 0 and the updated scrambling bit sequence is {0,0,0,0}irrespective of the data bit sequence. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {0,0,0,0} \right\}} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \right)}*1}}\end{matrix}$

In certain embodiments, if s_(l)=−1, then the original scrambling bitsequence is {1,1,0,0}. Thus, the scrambling-XOR-bit is 0 and theresult-bit-1 is 0 and the updated scrambling bit sequence is {1,1,0,0}irrespective of the data bit sequence. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {1,1,0,0} \right\}} \right)}} \\{= {\frac{1}{\sqrt{2}}\begin{Bmatrix}{{\left( {1 - {2\left( {1 - b_{0}} \right)}} \right)\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack} +} \\{{j\left( {1 - {2\left( {1 - b_{1}} \right)}} \right)}\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {{- \frac{1}{\sqrt{2}}}\begin{Bmatrix}{{\left( {1 - {2b_{0}}} \right)\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack} +} \\{{j\left( {1 - {2b_{1}}} \right)}\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \right)}*{- 1}}}\end{matrix}$

In certain embodiments, s_(l)=j with the following relationship:

$\begin{matrix}{{{M\left( \overset{\rightarrow}{c} \right)}*s_{l}} = {\frac{1}{\sqrt{10}}\begin{Bmatrix}{{{j\left( {1 - {2b_{0}}} \right)}\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack} -} \\{\left( {1 - {2b_{1}}} \right)\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {\frac{1}{\sqrt{10}}\begin{Bmatrix}{{\left( {1 - {2\left( {1 - b_{1}} \right)}} \right)\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack} +} \\{{j\left( {1 - {2b_{0}}} \right)}\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2}} \right\} \right)}}\end{matrix}$

Then, in further embodiments, the original scrambling bit sequence {a₀,a₁, a₂, a₃} is {1,0,0,0}. Thus, the scrambling-XOR-bit is 1. Also, whenb₀=b₁,b₂=b₃ (e.g., {b₀,b₁,b₂,b₃}={0,0,0,0} or {0,0,1,1} or d, then thedata-XOR-bit-1 and data-XOR-bit-2, are both 0, and the result-bit-1 andresult-bit-2 are both 0. Thus, the updated scrambling bit sequence is{1,0,0,0} and the scrambled bit sequence of this symbol is {1−b₀, b₁,b₂, b₃}, which can be modulated to a symbol equivalent to the symbolmodulated by {b₀,b₁,b₂, b₃} and multiplied with j. This may be expressedas follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {1,0,0,0} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},b_{0},b_{2},b_{3}} \right\} \right)}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2}} \right\} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \right)}*j}}\end{matrix}$

However, when b₀=1−b₁, b₂=b₃ (e.g., {b₀, b₁, b₂, b₃}={1,0,0,0} or{1,0,1,1} or {0,1,0,0} or {0,1,1,1}), then the data-XOR-bit-1 anddata-XOR-bit-2 are 1 and 0 respectively, and the result-bit-1 andresult-bit-2 are 1 and 0 respectively. Thus, the updated scrambling bitsequence is {0,1,0,0} and the scrambled bit sequence of this symbol is{1−b₀,b₁,b₂,b₃}, which can be modulated to a symbol equivalent to thesymbol modulated by {b₀, b₁, b₂, b₃} and multiplied with j. This may beexpressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {1,0,0,0} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},b_{0},b_{2},b_{3}} \right\} \right)}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2}} \right\} \right)}} \\{= {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \right)}*j}}\end{matrix}$

However, when b₀=b₁, b₂=1−b₃ (e.g., {b₀, b₁, b₂, b₃ }={0,0,0,1} or{0,0,1,0} or {1,1,0,1} or {1,1,1,0}), then the data-XOR-bit-1 anddata-XOR-bit-2 are 0 and 1 respectively, and the result-bit-1 andresult-bit-2 are 0 and 1 respectively. Thus, the updated scrambling bitsequence is {1,0,1,1} and the scrambled bit sequence of this symbol is{1−b₀, b₁, 1−b₂, 1−b₃}, which can be modulated to a symbol equivalent tothe symbol modulated by {b₀, b₁, b₂, b₃} and multiplied with j. This maybe expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {1,0,1,1} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},b_{1},{1 - b_{2}},{1 - b_{3}}} \right\} \right)}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*j} \right.}}\end{matrix}$

However, when b₀=1−b₁,b₂=1−b₃ (e.g., {b₀,b₁,b₂,b₃}={0,1,0,1} or{0,1,1,0} or {1,0,0,1} or {1,0,1,0}), then the data-XOR-bit-1 anddata-XOR-bit-2, are both 1, and the result-bit-1 and result-bit-2 areboth 1. Thus, the updated scrambling bit sequence is {0,1,1,1} and thescrambled bit sequence of this symbol is {b₀, 1−b₁, 1−b₂, 1−b₃}, whichcan be modulated to a symbol equivalent to the symbol modulated by {b₀,b₁, b₂, b₃} and multiplied with j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {0,1,1,1} \right\}} \right)}} \\{= {M\left( \left\{ {b_{0},{1 - b_{1}},{1 - b_{2}},{1 - b_{3}}} \right\} \right)}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*j} \right.}}\end{matrix}$

In certain embodiments, s_(l)=−j with the following relationship:

$\begin{matrix}{{{M\left( \overset{\rightarrow}{c} \right)}*s_{l}} = {\frac{1}{\sqrt{10}}\begin{Bmatrix}{{- {{j\left( {1 - {2b_{0}}} \right)}\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack}} +} \\{\left( {1 - {2b_{1}}} \right)\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {\frac{1}{\sqrt{10}}\begin{Bmatrix}{{\left( {1 - {2b_{1}}} \right)\left\lbrack {2 - \left( {1 - {2b_{3}}} \right)} \right\rbrack} +} \\{{j\left( {1 - {2\left( {1 - b_{0}} \right)}} \right)}\left\lbrack {2 - \left( {1 - {2b_{2}}} \right)} \right\rbrack}\end{Bmatrix}}} \\{= {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2}} \right\} \right)}}\end{matrix}$

Then, in further embodiments, the original scrambling bit sequence {a₀,a₁,a₂, a₃} is {0,1,0,0}, so the scrambling-XOR-bit is 1. Also, if b₀=b₁,b₂=b₃ (e.g., {b₀, b₁, b₂, b₃}={0,0,0,0} or {0,0,1,1} or {1,1,0,0} or{1,1,1,1}), then the data-XOR-bit-1 and data-XOR-bit-2, are both 0, andthe result-bit-1 and result-bit-2 are both 0. Thus, the updatedscrambling bit sequence is {0,1,0,0} and the scrambled bit sequence ofthis symbol is {b₀, 1−b₁,b₂,b₃}, which can be modulated to a symbolequivalent to the symbol modulated by {b₀, b₁, b₂, b₃} and multipliedwith −j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {0,1,0,0} \right\}} \right)}} \\{= {M\left( \left\{ {b_{0},{1 - b_{0}},b_{2},b_{3}} \right\} \right)}} \\{= {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*\left( {- j} \right)} \right.}}\end{matrix}$

However, when b₀=1−b₁,b₂=b₃ (e.g., {b₀, b₁,b₂, b₃}={0,1,0,0} or{0,1,1,1} or {1,0,0,0} or {1,0,1,1}), then the data-XOR-bit-1 anddata-XOR-bit-2 are 1 and 0 respectively, and the result-bit-1 andresult-bit-2 are 1 and 0 respectively. Thus, the updated scrambling bitsequence is {1,0,0,0} and the scrambled bit sequence of this symbol is{1−b₀,b₁,b₂,b₃}, which can be modulated to a symbol equivalent to thesymbol modulated by {b₀, b₁,b₂,b₃ } and multiplied with −j. This may beexpressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {1,0,0,0} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3}} \right\} \right)}} \\{= {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*\left( {- j} \right)} \right.}}\end{matrix}$

However, when b₀=b₁, b₂=1−b₃ (e.g., {b₀, b₁, b₂, b₃}={0,0,0,1} or{0,0,1,0} or {1,1,0,1} or {1,1,1,0}), then the data-XOR-bit-1 anddata-XOR-bit-2 are 0 and 1 respectively, and the result-bit-1 andresult-bit-2 are 0 and 1 respectively. Thus, the updated scrambling bitsequence is {0,1,1,1} and the scrambled bit sequence of this symbol is{b₀, 1−b₁, 1−b₂, 1−b₃}, which can be modulated to a symbol equivalent tothe symbol modulated by {b₀, b₁, b₂, b₃} and multiplied with −j. Thismay be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {0,1,1,1} \right\}} \right)}} \\{= {M\left( \left\{ {b_{0},{1 - b_{1}},{1 - b_{2}},{1 - b_{3}}} \right\} \right)}} \\{= {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*\left( {- j} \right)} \right.}}\end{matrix}$

However, when b₀=1−b₁, b₂=1−b₃ (e.g., {b₀, b₁, b₂ b₃}={0,1,0,1} or{0,1,1,0} or {1,0,0,1} or {1,0,1,0}), then the data-XOR-bit-1 anddata-XOR-bit-2 are both 1, and the result-bit-1 and result-bit-2 areboth 1. Thus, the updated scrambling bit sequence is {1,0,1,1} and thescrambled bit sequence of this symbol is {1−b₀, b₁, 1−b₂, 1−b₃}, whichcan be modulated to a symbol equivalent to the symbol modulated by {b₀,b₁, b₂, b₃} and multiplied with −j. This may be expressed as follows:

$\begin{matrix}{{M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3}} \right\}} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2}} \right\} \oplus \left\{ {1,0,1,1} \right\}} \right)}} \\{= {M\left( \left\{ {{1 - b_{0}},b_{1},{1 - b_{2}},{1 - b_{3}}} \right\} \right)}} \\{= {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2}} \right\} \right)}} \\{= {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3}} \right\}*\left( {- j} \right)} \right.}}\end{matrix}$

FIG. 8 is an illustration of a bit to symbol mapping for a 64 statequadrature amplitude modulation (64QAM) constellation used in updatedscrambling bit sequence processing, in accordance with some embodiments.The 64QAM constellation 800 denotes having each six consecutive codedbinary bits {right arrow over (c)}={b₀, b₁, b₂, b₃, b₄, b₅} mapped toone symbol, as expressed with the following equation:

${M\left( \overset{\rightarrow}{c} \right)} = {\frac{1}{\sqrt{42}}{\left\{ {{\left( {1 - {2b_{0}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack} + {{j\left( {1 - {2b_{1}}} \right)}\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack}} \right\}.}}$

In the above equation, b₀ denotes the sign of the real part of thecomplex-valued modulation symbol, b₁ denotes the sign of the imaginarypart, b₂ and b₄ are used to distinguish different coefficients of thereal part (e.g., the columns on the constellation), b₃ and b₅ are usedto distinguish different coefficients of the imaginary part (e.g., therows on the constellation) of the complex-valued modulation symbol. Forexample, the scrambling bit sequence corresponding to 64QAM withspreading value{1}, {−1},{j}, {−j} is {0,0,0,0,0,0}, {1,1,0,0,0,0},{1,0,0,0,0,0} and {0,1,0,0,0,0}.

In certain embodiments, when s_(l)=1, then the original scrambling bitsequence is {0,0,0,0,0,0}, so the scrambling-XOR-bit is 0 and theresult-bit-1, result-bit-2 and result-bit-3 all are all 0 and theupdated scrambling bit sequence is {0,0,0,0,0,0} irrespective of thedata bit sequence. This may be expressed as follows:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{\sim}{b}}_{4},{\overset{\sim}{b}}_{5}} \right\} \right)} = {\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3},{\overset{\_}{a}}_{4},{\overset{\_}{a}}_{5}} \right\}} \right) = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {0,0,0,0,0,0} \right\}} \right)} = {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right) \right\}}*1}}}$

In certain embodiments, s_(l)=−1 with the following relationship:

$\begin{matrix}{{{M\left( \overset{\rightarrow}{c} \right)}*s_{l}} = {{- \frac{1}{\sqrt{42}}}\begin{Bmatrix}{{\left( {1 - {2b_{0}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack} -} \\{{j\left( {1 - {2b_{1}}} \right)}\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack}\end{Bmatrix}}} \\{= {\frac{1}{\sqrt{42}}\begin{Bmatrix}{{\left( {1 - {2\left( {1 - b_{0}} \right)}} \right)\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack} +} \\{{j\left( {1 - {2\left( {1 - b_{1}} \right)}} \right)}\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack}\end{Bmatrix}}} \\{= {M\left( \left\{ {{1 - b_{0}},{1 - b_{1}},b_{2},b_{3},b_{4},b_{5}} \right\} \right)}}\end{matrix}$

Then, in further embodiments, the original scrambling bit sequence is{1,1,0,0,0,0}, so the scrambling-XOR-bit is 0 and the result-bit-1,result-bit-2 and result-bit-3 are all 0 and the updated scrambling bitsequence is {1,1,0,0,0,0} irrespective of the data bit sequence. Thismay be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{\sim}{b}}_{4},{\overset{\sim}{b}}_{5}} \right\} \right)} = {\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3},{\overset{\_}{a}}_{4},{\overset{\_}{a}}_{5}} \right\}} \right) = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {1,1,0,0,0,0,} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},{1 - b_{1}},b_{2},b_{3},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right) \right\}}*\left( {- 1} \right)}}}}$

In certain embodiments, s_(l)=j with the following relationship:

$\begin{matrix}{{{M\left( \overset{\rightarrow}{c} \right)}*s_{l}} = {j\frac{1}{\sqrt{42}}\begin{Bmatrix}{{\left( {1 - {2b_{0}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack} -} \\{\left( {1 - {2b_{1}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack}\end{Bmatrix}}} \\{= {\frac{1}{\sqrt{42}}\begin{Bmatrix}{{\left( {1 - {2\left( {1 - b_{1}} \right)}} \right)\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack} +} \\{{j\left( {1 - b_{0}} \right)}\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack}\end{Bmatrix}}} \\{= {M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)}}\end{matrix}$

Then, in further embodiments, the original scrambling bit sequence{a₀,a₁,a₂,a₃,a₄,a₅} is {1,0,0,0,0,0}, so the scrambling-XOR-bit is 1.Also, when b₀=b₁,b₂=b₃,b₄=b₅ (e.g., {b₀,b₁, b₂,b₃,b₄,b₅}={0,0,0,0,0,0}or {0,0,0,0,1,1} or {0,0,1,1,0,0} or {0,0,1,1,1,1} or {1,1,0,0,0,0} or{1,1,0,0,1,1} or {1,1,1,1,0,0} or {1,1,1,1,1,1}), then thedata-XOR-bit-1,data-XOR-bit-2 and data-XOR-bit-3 are all 0, and theresult-bit-1, result-bit-2 and result-bit-3 are all 0. Thus the updatedscrambling bit sequence is {1,0,0,0,0,0} and the scrambled bit sequenceof this symbol is {1−b₀, b₁, b₂,b₃,b₄, b₅}, which can be modulated to asymbol equivalent to the symbol modulated by {b₀, b₁,b₂, b₃, b₄, b₅} andmultiplied with j. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{\sim}{b}}_{4},{\overset{\sim}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3},{\overset{\_}{a}}_{4},{\overset{\_}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,0,0,0,0} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3},b_{4},b_{5}} \right) \right\}} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=b₁, b₂=b₃, b₄=1−b₅ (e.g., {b₀, b₁, b₂, b₃, b₄, b₅}={0,0,0,0,0,1} or {0,0,0,0,1,0} or {0,0,1,1,0,1} or {0,0,1,1,1,0} or{1,1,0,0,0,1} or {1,1,0,0,1,0} or {1,1,1,1,0,1} or {1,1,1,1,1,0}), thenthe updated scrambling bit sequence is {1,0,0,0,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{\sim}{b}}_{4},{\overset{\sim}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3},{\overset{\_}{a}}_{4},{\overset{\_}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,0,0,1,1} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right) \right\}} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=b₁, b₂=1−b₃, b₄=b₅ (e.g., {b₀, b₁, b₂, b₃, b₄, b₅}={0,0,0,1,0,0} or {0,0,0,1,1,1} or {0,0,1,0,0,0} or {0,0,1,0,1,1} or{1,1,0,1,0,0} or {1,1,0,1,1,1} or {1,1,1,0,0,0} or {1,1,1,0,1,1}), thenthe updated scrambling bit sequence is {1,0,1,1,0,0}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{\sim}{b}}_{4},{\overset{\sim}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{\_}{a}}_{0},{\overset{\_}{a}}_{1},{\overset{\_}{a}}_{2},{\overset{\_}{a}}_{3},{\overset{\_}{a}}_{4},{\overset{\_}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,1,1,0,0} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right) \right\}} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=b₁,b₂=1−b₃, b₄=1−b₅ (e.g.,b₀,b₁,b₂,b₃,b₄,b₅={0,0,0,1,0,1} or {0,0,0,1,1,0} or {0,0,1,0,0,1} or{0,0,1,0,1,0} or {1,1,0,1,0,1} or {1,1,0,1,1,0} or {1,1,1,0,0,1} or{1,1,1,0,1,0}), then the updated scrambling bit sequence is{1,0,1,1,1,1}. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,1,1,1,1} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},{1 - b_{2}},{1 - b_{3}},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=1−b₁,b₂=b₃, b₄=b₅ (e.g., {b₀,b₁,b₂,b₃,b₄,b₅}={0,1,0,0,0,0} or {0,1,0,0,1,1} or {0,1,1,1,0,0} or {0,1,1,1,1,1} or{1,0,0,0,0,0} or {1,0,0,0,1,1} or {1,0,1,1,0,0} or {1,0,1,1,1,1}), thenthe updated scrambling bit sequence is {0,1,0,0,0,0}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,0,0,0,0} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},b_{2},b_{3},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=1−b₁, b₂=b₃, b₄=1−b₅ (e.g., {b₀, b₁,b₂, b₃, b₄,b₅}={0,1,0,0,0,1} or {0,1,0,0,1,0} or {0,1,1,1,0,1} or {0,1,1,1,1,0} or{1,0,0,0,0,1} or {1,0,0,0,1,0} or {1,0,1,1,0,1} or {1,0,1,1,1,0}), thenthe updated scrambling bit sequence is {0,1,0,0,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,0,0,1,1} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=1−b₁,b₂=1−b₃, b₄=1−b₅ (e.g., {b₀,b₁, b₂,b₃,b₄,b₅}={0,1,0,1,0,0} or {0,1,0,1,1,1} or {0,1,1,0,0,0} or {0,1,1,0,1,1}or {1,0,0,1,0,0} or {1,0,0,1,1,1} or {1,0,1,0,0,0} or {1,0,1,0,1,1}),then the updated scrambling bit sequence is {0,1,1,1,0,0}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,1,1,0,0} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},{1 - b_{2}},{1 - b_{3}},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

However, when b₀=1−b₁,b₂=1−b₃,b₄=1−b₅ (e.g., {b₀,b₁,b₂,b₃,b₄,b₅}={0,1,0,1,0,1} or {0,1,0,1,1,0} or {0,1,1,0,0,1} or{0,1,1,0,1,0} or {1,0,0,1,0,1} or {1,0,0,1,1,0} or {1,0,1,0,0,1} or{1,0,1,0,1,0}), then the updated scrambling bit sequence is{0,1,1,1,1,1}. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,1,1,1,1} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},{1 - b_{2}},{1 - b_{3}},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {{1 - b_{1}},b_{0},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*j} \right.}}}}}$

In certain embodiments, s_(l)=−j with the following relationship:

${{M\left( \overset{\rightarrow}{c} \right)}*s_{l}} = {{{- j}\frac{1}{\sqrt{42}}\left\{ {{\left( {1 - {2b_{0}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack} + {\left( {1 - {2b_{1}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack}} \right\}} = {{\frac{1}{\sqrt{42}}\left\{ {{\left( {1 - {2b_{1}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {2 - \left( {1 - {2b_{5}}} \right)} \right\rbrack}} \right\rbrack} + {{j\left( {1 - {2\left( {1 - b_{0}} \right)}} \right)}\left\lbrack {4 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {2 - \left( {1 - {2b_{4}}} \right)} \right\rbrack}} \right\rbrack}} \right\}} = {M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)}}}$

Then, in further embodiments, the original scrambling bit sequence {a₀,a₁, a₂, a₃, a₄, a₅} is {0,1,0,0,0,0}, so the scrambling-XOR-bit is 1.Also, when b₀=b₁,b₂=b₃,b₄=b₅ (e.g., {b₀, b₁, b₂,b₃,b₄,b₅} {0,0,0,0,0,0}or {0,0,0,0,1,1} or {0,0,1,1,0,0} or {0,0,1,1,1,1} or {1,1,0,0,0,0} or{1,1,1,0,0,1,1} or {1,1,1,1,0,0} or {1,1,1,1,1,1}), then thedata-XOR-bit-1,data-XOR-bit-2 and data-XOR-bit-3 are all 0, and theresult-bit-1, result-bit-2 and result-bit-3 are all 0. Thus the updatedscrambling bit sequence is {0,1,0,0,0,0} and the scrambled bit sequenceof this symbol is {b₀,1−b₁,b₂,b₃,b₄,b₅}, which can be modulated to asymbol equivalent to the symbol modulated by {b₀, b₁, b₂, b₃, b₄, b₅}and multiplied with −j. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,0,0,0,0} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},b_{2},b_{3},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=b₁, b₂=b₃, b₄=1−b₅ (e.g., {b₀, b₁, b₂, b₃, b₄, b₅}{0,0,0,0,0,1} or {0,0,0,0,1,0} or {0,0,1,1,0,1} or {0,0,1,1,1,0} or{1,1,0,0,0,1} or {1,1,0,0,1,0} or {1,1,1,1,0,1} or {1,1,1,1,1,0}), thenthe updated scrambling bit sequence is {0,1,0,0,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,0,0,1,1} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=b₁,b₂=1−b₃,b₄=b₅ (e.g., {b₀,b₁,b₂,b₃,b₄,b₅}={0,0,0,1,0,0} or {0,0,0,1,1,1} or {0,0,1,0,0,0} or{0,0,1,0,1,1} or {1,1,0,1,0,0} or {1,1,0,1,1,1} or {1,1,1,0,0,0} or{1,1,1,0,1,1}), then the updated scrambling bit sequence is{0,1,1,1,0,0}. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,1,1,0,0} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=b₁, b₂=1−b₃, b₄=1−b₅ (e.g., {b₀, b₁, b₂, b₃, b₄,b₅}={0,0,0,1,0,1} or {0,0,0,1,1,0} or {0,0,1,0,0,1} or {0,0,1,0,1,0} or{1,1,0,1,0,1} or {1,1,0,1,1,0} or {1,1,1,0,0,1} or {1,1,1,0,1,0}), thenthe updated scrambling bit sequence is {0,1,1,1,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {0,1,1,1,1,1} \right\}} \right)} = {{M\left( \left\{ {b_{0},{1 - b_{1}},{1 - b_{2}},{1 - b_{3}},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=1−b₁,b₂=b₃,b₄=b₅ (e.g., {b₀,b₁,b₂,b₃,b₄,b₅}={0,1,0,0,0,0} or {0,1,0,0,1,1} or {0,1,1,1,0,0} or{0,1,1,1,1,1} or {1,0,0,0,0,0} or {1,0,0,0,1,1} or {1,0,1,1,0,0} or{1,0,1,1,1,1}), then the updated scrambling bit sequence is{1,0,0,0,0,0}. This may be expressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,0,0,0,0} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=1−b₁,b₂=b₃,b₄=1−b₅ (e.g., {b₀, b₁,b₂,b₃,b₄,b₅}={0,1,0,0,0,1} or {0,1,0,0,1,0} or {0,1,1,1,0,1} or {0,1,1,1,1,0} or{1,0,0,0,0,1} or {1,0,0,0,1,0} or {1,0,1,1,0,1} or {1,0,1,1,1,0}), thenthe updated scrambling bit sequence is {1,0,0,0,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,0,0,1,1} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},b_{2},b_{3},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=1−b₁, b₂=1−b₃, b₄=b₅ (e.g., {b₀, b₁, b₂, b₃, b₄,b₅}={0,1,0,1,0,0} or {0,1,0,1,1,1} or {0,1,1,0,0,0} or {0,1,1,0,1,1} or{1,0,0,1,0,0} or {1,0,0,1,1,1} or {1,0,1,0,0,0} or {1,0,1,0,1,1}), thenthe updated scrambling bit sequence is {1,0,1,1,0,0}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,1,1,0,0} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},{1 - b_{2}},{1 - b_{3}},b_{4},b_{5}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

However, when b₀=1−b₁, b₂=1−b₃, b₄=1−b₅ (e.g., {b₀, b₁, b₂, b₃, b₄,b₅}={0,1,0,1,0,1} or {0,1,0,1,1,0} or {0,1,1,0,0,1} or {0,1,1,0,1,0} or{1,0,0,1,0,1} or {1,0,0,1,1,0} or {1,0,1,0,0,1} or {1,0,1,0,1,0}), thenthe updated scrambling bit sequence is {1,0,1,1,1,1}. This may beexpressed as:

${M\left( \left\{ {{\overset{\sim}{b}}_{0},{\overset{\sim}{b}}_{1},{\overset{\sim}{b}}_{2},{\overset{\sim}{b}}_{3},{\overset{˜}{b}}_{4},{\overset{˜}{b}}_{5}} \right\} \right)} = {{M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\} \oplus \left\{ {{\overset{¯}{a}}_{0},\ {\overset{¯}{a}}_{1},{\overset{¯}{a}}_{2},{\overset{¯}{a}}_{3},{\overset{¯}{a}}_{4},{\overset{¯}{a}}_{5}} \right\}} \right)} = {{M\left( {\left\{ {b_{0},b_{0},b_{2},b_{2},b_{4},b_{5}} \right\} \oplus \left\{ {1,0,1,1,1,1} \right\}} \right)} = {{M\left( \left\{ {{1 - b_{0}},b_{1},{1 - b_{2}},{1 - b_{3}},{1 - b_{4}},{1 - b_{5}}} \right\} \right)} = {{M\left( \left\{ {b_{1},{1 - b_{0}},b_{3},b_{2},b_{5},b_{4}} \right\} \right)} = {M\left( {\left\{ {b_{0},b_{1},b_{2},b_{3},b_{4},b_{5}} \right\}*\left( {- j} \right)} \right.}}}}}$

Although certain implementations of either an updated scrambling bitsequence processing or updated data bit sequence processing arediscussed above, updated scrambling bit sequence processing or updateddata bit sequence processing may be implemented in any of a number ofadditional ways as desired for different applications in variousembodiments. For example, updated scrambling bit sequence processing mayreference a 256 state QAM (256QAM) where each six consecutive codedbinary bits {right arrow over (c)}={b₀, b₁, b₂, b₃, b₄, b₅, b₆, b₇} aremapped to one symbol as expressed with the following equation:

${M\left( \overset{\rightarrow}{c} \right)} = {\frac{1}{\sqrt{170}}{\left\{ {{\left( {1 - {2b_{0}}} \right)\left\lbrack {8 - {\left( {1 - {2b_{2}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{4}}} \right)\left\lbrack {2 - \left( {1 - {2b_{6}}} \right)} \right\rbrack}} \right\rbrack}} \right\rbrack} + {{j\left( {1 - {2b_{1}}} \right)}\left\lbrack {8 - {\left( {1 - {2b_{3}}} \right)\left\lbrack {4 - {\left( {1 - {2b_{5}}} \right)\left\lbrack {2 - \left( {1 - {2b_{7}}} \right)} \right\rbrack}} \right\rbrack}} \right\rbrack}} \right\}.}}$

Also, in certain embodiments, the scrambling bit sequence correspondingto 256QAM to symbol multiplexing value{1}, {−1}, {j}, {−j} is{0,0,0,0,0,0}, {1,1,0,0,0,0,0,0}, {1,0,0,0,0,0,0,0} and{0,1,0,0,0,0,0,0}. As demonstrated above, further implementations ofupdated scrambling bit sequence processing may scramble a data bitsequence produce a scrambled data bit sequence that is then modulated toproduce a symbol sequence. This symbol sequence may be equivalent toanother symbol sequence produced by having the same data bit sequencebeing directly modulated and symbol spread without symbol levelscrambling within the domain of {1}, {−1}, {j}, {−j}.

While various embodiments of the invention have been described above, itshould be understood that they have been presented by way of exampleonly, and not by way of limitation. Likewise, the various diagrams maydepict an example architectural or configuration, which are provided toenable persons of ordinary skill in the art to understand exemplaryfeatures and functions of the invention. Such persons would understand,however, that the invention is not restricted to the illustrated examplearchitectures or configurations, but can be implemented using a varietyof alternative architectures and configurations. Additionally, as wouldbe understood by persons of ordinary skill in the art, one or morefeatures of one embodiment can be combined with one or more features ofanother embodiment described herein. Thus, the breadth and scope of thepresent disclosure should not be limited by any of the above-describedexemplary embodiments.

It is also understood that any reference to an element or embodimentherein using a designation such as “first,” “second,” and so forth doesnot generally limit the quantity or order of those elements. Rather,these designations can be used herein as a convenient means ofdistinguishing between two or more elements or instances of an element.Thus, a reference to first and second elements does not mean that onlytwo elements can be employed, or that the first element must precede thesecond element in some manner.

Additionally, a person having ordinary skill in the art would understandthat information and signals can be represented using any of a varietyof different technologies and techniques. For example, data,instructions, commands, information, signals, bits and symbols, forexample, which may be referenced in the above description can berepresented by voltages, currents, electromagnetic waves, magneticfields or particles, optical fields or particles, or any combinationthereof.

A person of ordinary skill in the art would further appreciate that anyof the various illustrative logical blocks, modules, processors, means,circuits, methods and functions described in connection with the aspectsdisclosed herein can be implemented by electronic hardware (e.g., adigital implementation, an analog implementation, or a combination ofthe two), firmware, various forms of program or design codeincorporating instructions (which can be referred to herein, forconvenience, as “software” or a “software module), or any combination ofthese techniques. To clearly illustrate this interchangeability ofhardware, firmware and software, various illustrative components,blocks, modules, circuits, and steps have been described above generallyin terms of their functionality. Whether such functionality isimplemented as hardware, firmware or software, or a combination of thesetechniques, depends upon the particular application and designconstraints imposed on the overall system. Skilled artisans canimplement the described functionality in various ways for eachparticular application, but such implementation decisions do not cause adeparture from the scope of the present disclosure.

Furthermore, a person of ordinary skill in the art would understand thatvarious illustrative logical blocks, modules, devices, components andcircuits described herein can be implemented within or performed by anintegrated circuit (IC) that can include a general purpose processor, adigital signal processor (DSP), an application specific integratedcircuit (ASIC), a field programmable gate array (FPGA) or otherprogrammable logic device, or any combination thereof. The logicalblocks, modules, and circuits can further include antennas and/ortransceivers to communicate with various components within the networkor within the device. A general purpose processor can be amicroprocessor, but in the alternative, the processor can be anyconventional processor, controller, or state machine. A processor canalso be implemented as a combination of computing devices, e.g., acombination of a DSP and a microprocessor, a plurality ofmicroprocessors, one or more microprocessors in conjunction with a DSPcore, or any other suitable configuration to perform the functionsdescribed herein.

If implemented in software, the functions can be stored as one or moreinstructions or code on a computer-readable medium. Thus, the steps of amethod or algorithm disclosed herein can be implemented as softwarestored on a computer-readable medium. Computer-readable media includesboth computer storage media and communication media including any mediumthat can be enabled to transfer a computer program or code from oneplace to another. A storage media can be any available media that can beaccessed by a computer. By way of example, and not limitation, suchcomputer-readable media can include RAM, ROM, EEPROM, CD-ROM or otheroptical disk storage, magnetic disk storage or other magnetic storagedevices, or any other medium that can be used to store desired programcode in the form of instructions or data structures and that can beaccessed by a computer.

In this document, the term “module” as used herein, refers to software,firmware, hardware, and any combination of these elements for performingthe associated functions described herein. Additionally, for purpose ofdiscussion, the various modules are described as discrete modules;however, as would be apparent to one of ordinary skill in the art, twoor more modules may be combined to form a single module that performsthe associated functions according embodiments of the invention.

Additionally, one or more of the functions described in this documentmay be performed by means of computer program code that is stored in a“computer program product”, “computer-readable medium”, and the like,which is used herein to generally refer to media such as, memory storagedevices, or storage unit. These, and other forms of computer-readablemedia, may be involved in storing one or more instructions for use byprocessor to cause the processor to perform specified operations. Suchinstructions, generally referred to as “computer program code” (whichmay be grouped in the form of computer programs or other groupings),which when executed, enable the computing system to perform the desiredoperations.

Additionally, memory or other storage, as well as communicationcomponents, may be employed in embodiments of the invention. It will beappreciated that, for clarity purposes, the above description hasdescribed embodiments of the invention with reference to differentfunctional units and processors. However, it will be apparent that anysuitable distribution of functionality between different functionalunits, processing logic elements or domains may be used withoutdetracting from the invention. For example, functionality illustrated tobe performed by separate processing logic elements, or controllers, maybe performed by the same processing logic element, or controller. Hence,references to specific functional units are only references to asuitable means for providing the described functionality, rather thanindicative of a strict logical or physical structure or organization.

Various modifications to the implementations described in thisdisclosure will be readily apparent to those skilled in the art, and thegeneral principles defined herein can be applied to otherimplementations without departing from the scope of this disclosure.Thus, the disclosure is not intended to be limited to theimplementations shown herein, but is to be accorded the widest scopeconsistent with the novel features and principles disclosed herein, asrecited in the claims below.

What is claimed is:
 1. A method performed by a communication device, comprising: encoding user data to produce a first data bit sequence; generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence; and transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequence.
 2. The method of claim 1, further comprising: performing an exclusive OR (XOR) operation on two adjacent most significant bits of the first scrambling bit sequence to produce a scrambling bit value; performing the XOR operation on each two adjacent bits of the first data bit sequence to produce a second data bit sequence; and performing an AND operation on the scrambling bit value and the second data bit sequence to produce the result bit sequence.
 3. The method of claim 2, further comprising: performing the XOR operation on the result bit sequence with each corresponding two adjacent bits of the first scrambling bit sequence to produce an updated scrambling bit sequence; and scrambling the first data bit sequence with the updated scrambling bit sequence to produce the scrambled data bit sequence.
 4. The method of claim 2, further comprising: performing the XOR operation on the result bit sequence with each corresponding two adjacent bits of the first data bit sequence to produce an updated data bit sequence; and scrambling the updated data bit sequence with the first scrambling bit sequence to produce the scrambled data bit sequence.
 5. The method of claim 2, further comprising: producing the first data bit sequence by duplicating an initial data bit sequence a number of times to achieve a length associated with a symbol spreading value.
 6. The method of claim 2, wherein the first data bit sequence is associated with a single symbol.
 7. The method of claim 2, further comprising: modulating the scrambled data bit sequence into multiple symbols.
 8. The method of claim 2, further comprising: modulating the scrambled data bit sequence using quadrature phase shift keying (QPSK).
 9. The method of claim 2, further comprising: modulating the scrambled data bit sequence using a quadrature amplitude modulation (QAM) complex-valued modulation constellation, which is symmetrical about two axes; wherein the QAM complex-valued modulation constellation is associated with least one of: a 16QAM, a 64QAM, a 256QAM, and a 1024QAM.
 10. A method performed by a communication node, comprising: encoding user data to produce a first data bit sequence; generating a result bit sequence based on a first scrambling bit sequence and the first data bit sequence; and transmitting a signal based on a scrambled data bit sequence scrambled with the result bit sequence.
 11. The method of claim 10, further comprising: performing an exclusive OR (XOR) operation on two adjacent most significant bits of the first scrambling bit sequence to produce a scrambling bit value; performing the XOR operation on each two adjacent bits of the first data bit sequence to produce a second data bit sequence; and performing an AND operation on the scrambling bit value and the second data bit sequence to produce the result bit sequence.
 12. The method of claim 11, further comprising: performing the XOR operation on the result bit sequence with each corresponding two adjacent bits of the first scrambling bit sequence to produce an updated scrambling bit sequence; and scrambling the first data bit sequence with the updated scrambling bit sequence to produce the scrambled data bit sequence.
 13. The method of claim 11, further comprising: performing the XOR operation on the result bit sequence with each corresponding two adjacent bits of the first data bit sequence to produce an updated data bit sequence; and scrambling the updated data bit sequence with the first scrambling bit sequence to produce the scrambled data bit sequence.
 14. The method of claim 11, further comprising: producing the first data bit sequence by duplicating an initial data bit sequence a number of times to achieve a length associated with a symbol spreading value.
 15. The method of claim 11, wherein the first data bit sequence is associated with a single symbol.
 16. The method of claim 11, further comprising: modulating the scrambled data bit sequence into multiple symbols.
 17. The method of claim 11, further comprising: modulating the scrambled data bit sequence using quadrature phase shift keying (QPSK).
 18. The method of claim 11, further comprising: modulating the scrambled data bit sequence using a quadrature amplitude modulation (QAM) complex-valued modulation constellation, which is symmetrical about two axes; wherein the QAM complex-valued modulation constellation is associated with least one of: a 16QAM, a 64QAM, a 256QAM, and a 1024QAM.
 19. A non-transitory computer-readable medium having stored thereon computer-executable instructions for carrying out the method claim
 1. 20. A non-transitory computer-readable medium having stored thereon computer-executable instructions for carrying out the method claim
 10. 